U.S. Pat. No. 7,705,368 and Japanese Patent 4,284,689 (having inventors in common with the present inventors) disclose an efficient MOS-gated power switching device referred to as an insulated gate turn off device or an “IGTO” with both high current density and low ON voltage. U.S. Pat. No. 7,705,368 is incorporated herein by reference at least for its process description and description of the method of operation of the IGTO.
A cross-section of a portion of the IGTO of the '368 patent is shown in FIG. 1, while a top view of the gate area is shown in FIG. 2. FIG. 1 is a cross-section along line 1-1 in FIG. 2.
The conductive gate 12 of the IGTO is formed in a trench that has a “rectangular mesh” structure (FIG. 2) which surrounds the N+ emitter/source 14 and portions of the P− base/body 16 of the bipolar MOS transistor. The P− base/body 16 is also referred to as a P-well. A forward voltage is applied between the metal drain electrode 18 and the metal source electrode 20. In one application, a load may be connected between the source electrode 20 and ground. A gate electrode 22 is used to bias the vertical gates 12. All the gates 12 are electrically connected together outside the field of FIG. 1. When the gates 12 are suitably positively biased, the effective base width of the vertical NPN transistor is reduced, increasing its beta, causing the product of the betas of the vertical NPN and PNP transistors to be greater than one, resulting in regenerative action. As a result, current flows between the source and drain electrodes with a low ON voltage.
In these cells, which are referred to as “active cells,” current flows vertically through the separate rectangular regions of the IGTO that are surrounded by the vertical gates 12. The individual rectangular regions conduct current in parallel, resulting in a device that has a low ON voltage and is able to conduct high current. However, the IGTO structure shown in FIGS. 1 and 2 has a relatively high capacitance, which impacts both switching speed and power dissipation. In addition, this structure has high saturation current, which is a disadvantage in some applications.
The capacitance between the gate (at one voltage) and the adjacent N+ source/P-body (at another voltage) is relatively high since the gate and source/body are separated by a thin gate oxide, and there is a relatively large “plate” area. The capacitance between the gate and the drain electrode is low due to their large separation.
In some applications, the customer requires a low input capacitance and/or a low saturation current.
What is needed is an improved IGTO with a lower capacitance and lower saturation current. A lower capacitance enables more rapid switching. Saturation current, in this context, means that the IGTO self-limits its current, typically to a level above the normal load current. Therefore, the IGTO may advantageously self-limit its current even if the load fails and becomes a short circuit. In an example, a low saturation current may provide the time needed for a driver circuit to sense an over-current condition and reduce the current to an acceptable level, since a lower current results in lower power dissipation. Hence, relatively low saturation currents may be desirable. It is also desirable that the input capacitance and saturation current be customizable for a particular customer without adding steps to the fabrication process.